[all-commits] [llvm/llvm-project] e00e20: [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e00e20a055fcd7386434f237784d845d5ddfc1b1
      https://github.com/llvm/llvm-project/commit/e00e20a055fcd7386434f237784d845d5ddfc1b1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-01 (Thu, 01 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div-pow2.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-arith-strict.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/float-arith-strict.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.

These instructions requires both register operands to be compressible
so I've only applied the hint if we already have a GPRC physical register
assigned for the other register operand.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D139079