[all-commits] [llvm/llvm-project] 6d1259: [CodeGen] Add new pass for late cleanup of redunda...

Thu Dec 1 10:22:03 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6d12599fd4134c1da63198c74a25490d28c733f6
      https://github.com/llvm/llvm-project/commit/6d12599fd4134c1da63198c74a25490d28c733f6
  Author: Jonas Paulsson <paulsson at linux.vnet.ibm.com>
  Date:   2022-12-01 (Thu, 01 Dec 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
    M llvm/include/llvm/CodeGen/MachinePassRegistry.def
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    M llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
    M llvm/test/CodeGen/ARM/jump-table-islands.ll
    M llvm/test/CodeGen/ARM/reg_sequence.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
    M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
    M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
    M llvm/test/CodeGen/PowerPC/cgp-select.ll
    M llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    A llvm/test/CodeGen/SystemZ/frame-28.mir
    M llvm/test/CodeGen/Thumb/frame-access.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
    M llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
    M llvm/test/CodeGen/X86/fast-isel-stackcheck.ll
    M llvm/test/CodeGen/X86/fshl.ll
    M llvm/test/CodeGen/X86/masked_load.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/shift-i128.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_extract.ll
    M llvm/test/CodeGen/X86/vec_shift5.ll
    M llvm/test/CodeGen/XCore/scavenging.ll

  Log Message:
  -----------
  [CodeGen] Add new pass for late cleanup of redundant definitions.

A new pass MachineLateInstrsCleanup is added to be run after PEI.

This is a simple pass that removes redundant and identical instructions
whenever found by scanning the MF once while keeping track of register
definitions in a map. These instructions are typically immediate loads
resulting from rematerialization, and address loads emitted by target in
eliminateFrameInde().

This is enabled by default, but a target could easily disable it by means of
'disablePass(&MachineLateInstrsCleanupID);'.

This late cleanup is naturally not "optimal" in removing instructions as it
is done by looking at phys-regs, but still quite effective. It would be
desirable to improve other parts of CodeGen and avoid these redundant
instructions in the first place, but there are no ideas for this yet.

Differential Revision: https://reviews.llvm.org/D123394

Reviewed By: RKSimon, foad, craig.topper, arsenm, asb