[all-commits] [llvm/llvm-project] 7899cc: [RISCV] Replace hardcoded constant with OPIVI.Valu...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7899cc3c4536f31b9988165ebb5fb2c649b377f4
      https://github.com/llvm/llvm-project/commit/7899cc3c4536f31b9988165ebb5fb2c649b377f4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-30 (Wed, 30 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

  Log Message:
  -----------
  [RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC


  Commit: df7ab6a52e302b63837a34a15e3f35455fea2929
      https://github.com/llvm/llvm-project/commit/df7ab6a52e302b63837a34a15e3f35455fea2929
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-30 (Wed, 30 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/branch.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

  Log Message:
  -----------
  [RISCV] Add ANDI to getRegAllocationHints.


Compare: https://github.com/llvm/llvm-project/compare/2bda5a62870d...df7ab6a52e30