[all-commits] [llvm/llvm-project] 7fea6f: [AArch64] Assembly support for VMSA

tmatheson-arm via All-commits all-commits at lists.llvm.org
Wed Nov 30 05:37:52 PST 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7fea6f2e0e606e5339c3359568f680eaf64aa306
      https://github.com/llvm/llvm-project/commit/7fea6f2e0e606e5339c3359568f680eaf64aa306
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2022-11-30 (Wed, 30 Nov 2022)

  Changed paths:
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Basic/Targets/AArch64.h
    A clang/test/Driver/aarch64-d128.c
    A clang/test/Driver/aarch64-lse128.c
    A clang/test/Driver/aarch64-the.c
    M llvm/include/llvm/Support/AArch64TargetParser.def
    M llvm/include/llvm/Support/AArch64TargetParser.h
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    M llvm/lib/Target/AArch64/AArch64SystemOperands.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
    M llvm/test/MC/AArch64/arm64-system-encoding.s
    A llvm/test/MC/AArch64/armv8.9a-the.s
    A llvm/test/MC/AArch64/armv9-mrrs.s
    A llvm/test/MC/AArch64/armv9-msrr.s
    A llvm/test/MC/AArch64/armv9-sysp.s
    A llvm/test/MC/AArch64/armv9.4-lse128.s
    M llvm/test/MC/AArch64/basic-a64-instructions.s
    M llvm/test/MC/AArch64/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/directive-arch_extension.s
    A llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt
    A llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt
    A llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt
    A llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt
    M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
    M llvm/unittests/Support/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Assembly support for VMSA

Virtual Memory System Architecture (VMSA)

This is part of the 2022 A-Profile Architecture extensions and adds support for
the following:

 - Translation Hardening Extension (FEAT_THE)
 - 128-bit Page Table Descriptors (FEAT_D128)
 - 56-bit Virtual Address (FEAT_LVA3)
 - Support for 128-bit System Registers (FEAT_SYSREG128)
 - System Instructions that can take 128-bit inputs (FEAT_SYSINSTR128)
 - 128-bit Atomic Instructions (FEAT_LSE128)
 - Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
 - Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
 - Memory Attribute Index Enhancement (FEAT_AIE)

New instructions added:
 - FEAT_SYSREG128 adds MRRS and MSRR.
 - FEAT_SYSINSTR128 adds the SYSP instruction and TLBIP aliases.
 - FEAT_LSE128 adds LDCLRP, LDSET, and SWPP instructions.
 - FEAT_THE adds the set of RCW* instructions.

Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

Contributors:
  Keith Walker
  Lucas Prates
  Sam Elliott
  Son Tuan Vu
  Tomas Matheson

Differential Revision: https://reviews.llvm.org/D138920




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