[all-commits] [llvm/llvm-project] fc0efb: [SDAG] Allow scalable vectors in ComputeNumSignBit...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fc0efb7e78b31263ad1601018de8399272a75e35
      https://github.com/llvm/llvm-project/commit/fc0efb7e78b31263ad1601018de8399272a75e35
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-11-29 (Tue, 29 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

  Log Message:
  -----------
  [SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)

I had reverted this before the holiday week because a problem was reported with a related change (D137140 - scalable vector known bits in DAG).  I had initially confused the two patches, and then decided to leave this reverted out an abundance of caution.  Now that we're through the holiday week, reapplying.

I also roled in fixes for several post commit review comments that hadn't landed with the original change.

Original commit message

This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137141