[all-commits] [llvm/llvm-project] 68057c: Add new vector types for LLVM

[Mateja Marjanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 68057c2b8d94d0426a72ad81b00b215f7b5650fa
      https://github.com/llvm/llvm-project/commit/68057c2b8d94d0426a72ad81b00b215f7b5650fa
  Author: Mateja Marjanovic <mateja.marjanovic at amd.com>
  Date:   2022-11-29 (Tue, 29 Nov 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  Add new vector types for LLVM

Add v9i32, v9f32, v10i32, v10f32, v11i32, v11f32, v12i32 and v12f32.

Differential Revision: https://reviews.llvm.org/D138136


  Commit: 595a08847a4b6e8d52c40715e2fa03e3d7f73189
      https://github.com/llvm/llvm-project/commit/595a08847a4b6e8d52c40715e2fa03e3d7f73189
  Author: Mateja Marjanovic <mateja.marjanovic at amd.com>
  Date:   2022-11-29 (Tue, 29 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
    M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
    M llvm/test/Analysis/CostModel/AMDGPU/arith-ssat.ll
    M llvm/test/Analysis/CostModel/AMDGPU/arith-usat.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
    M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
    M llvm/test/MC/AMDGPU/gfx1013.s
    M llvm/test/MC/AMDGPU/gfx1030_new.s
    M llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
    M llvm/test/MC/AMDGPU/gfx10_unsupported.s
    M llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
    M llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
    M llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
    M llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
    M llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt

  Log Message:
  -----------
  [AMDGPU] Add support for new LLVM vector types

Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205


Compare: https://github.com/llvm/llvm-project/compare/02ea3694a0a5...595a08847a4b