[all-commits] [llvm/llvm-project] 49cd18: Revert "[AArch64] Canonicalize ZERO_EXTEND to VSEL...

[Nicola Lancellotti via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 49cd18c55e963f903fc5adb264036e55d043c725
      https://github.com/llvm/llvm-project/commit/49cd18c55e963f903fc5adb264036e55d043c725
  Author: Nicola Lancellotti <nicola.lancellotti at arm.com>
  Date:   2022-11-28 (Mon, 28 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    R llvm/test/CodeGen/AArch64/predicated-add-sub-mul.ll

  Log Message:
  -----------
  Revert "[AArch64] Canonicalize ZERO_EXTEND to VSELECT"

This reverts commit 43fe14c056458501990c3db2788f67268d1bdf38.


  Commit: 1884ada741c90602a7dfa33867c68cd290838241
      https://github.com/llvm/llvm-project/commit/1884ada741c90602a7dfa33867c68cd290838241
  Author: Nicola Lancellotti <nicola.lancellotti at arm.com>
  Date:   2022-11-28 (Mon, 28 Nov 2022)

  Changed paths:
    A llvm/test/CodeGen/AArch64/predicated-add-sub.ll

  Log Message:
  -----------
  [AArch64] Pre-commit test for "Add patterns for SVE predicated add/sub and mov combine"


  Commit: 7bbfc6cd8c5e2cb162b7673f7b6b2303a7804845
      https://github.com/llvm/llvm-project/commit/7bbfc6cd8c5e2cb162b7673f7b6b2303a7804845
  Author: Nicola Lancellotti <nicola.lancellotti at arm.com>
  Date:   2022-11-28 (Mon, 28 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/predicated-add-sub.ll

  Log Message:
  -----------
  [AArch64] Add patterns for SVE predicated add/sub and mov combine

Differential Revision: https://reviews.llvm.org/D138570


Compare: https://github.com/llvm/llvm-project/compare/1ea66eefec8d...7bbfc6cd8c5e