[all-commits] [llvm/llvm-project] 79b582: [TargetLowering][AArch64] Teach DemandedBits about...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79b5829a155f256001ead535c358a1193cd0cbe8
      https://github.com/llvm/llvm-project/commit/79b5829a155f256001ead535c358a1193cd0cbe8
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2022-11-25 (Fri, 25 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

  Log Message:
  -----------
  [TargetLowering][AArch64] Teach DemandedBits about SVE count intrinsics

This allows DemandedBits to see that the SVE count intrinsics (CNTB,
CNTH, CNTW, CNTD) sans multiplier will only ever produce small
positive integers. The maximum value you could get here is 256, which
is CNTB on a machine with a 2048bit vector size (the maximum for SVE).

Using this various redundant operations (zexts, sexts, ands, ors, etc)
can be eliminated.

Differential Revision: https://reviews.llvm.org/D138424