[all-commits] [llvm/llvm-project] 241acc: [RISCV] Lower unmasked zero-stride vector load to ...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 241accea2a9d27ec284497d7555fe7f70164b39a
      https://github.com/llvm/llvm-project/commit/241accea2a9d27ec284497d7555fe7f70164b39a
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2022-11-24 (Thu, 24 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

  Log Message:
  -----------
  [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat)

So we have the opportunity to fold splat into .vx instruction as what
D101138 has done. If failed, we can select zero-stride vector load
again.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D138101