[all-commits] [llvm/llvm-project] 6d4ab6: [LLDB][RISCV] Add RV32F instruction support for Em...

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6d4ab6d921792125969e5f917b84cc810a1ba95c
      https://github.com/llvm/llvm-project/commit/6d4ab6d921792125969e5f917b84cc810a1ba95c
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2022-11-23 (Wed, 23 Nov 2022)

  Changed paths:
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
    M lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h
    M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
    M lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

  Log Message:
  -----------
  [LLDB][RISCV] Add RV32F instruction support for EmulateInstructionRISCV

Add:

- RV32F instruction set.
- corresponding unittests.

Further work:

- RV32FC, RV64F and RV64FC instructions support.
- update execution exceptions to fcsr register in RVM instructions.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D138447