[all-commits] [llvm/llvm-project] 7fbdee: Add RegionBranchOpInterface for AffineIf Op

[akshaybaviskar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7fbdee3e29203f2ffd1996c2919096e0bfe7c93b
      https://github.com/llvm/llvm-project/commit/7fbdee3e29203f2ffd1996c2919096e0bfe7c93b
  Author: Akshay Baviskar <akshay at polymagelabs.com>
  Date:   2022-11-23 (Wed, 23 Nov 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
    M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
    M mlir/test/Dialect/Bufferization/Transforms/buffer-deallocation.mlir

  Log Message:
  -----------
  Add RegionBranchOpInterface for AffineIf Op

Adds RegionBranchOpInterface for AffineIf Op and tests it
using buffer deallocation pass.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D130962