[all-commits] [llvm/llvm-project] 2dfe76: [CostModel][X86] Add CostKinds test coverage for s...

[HaohaiWen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2dfe76e989877d3992bf52971f27ad4ae5064a6d
      https://github.com/llvm/llvm-project/commit/2dfe76e989877d3992bf52971f27ad4ae5064a6d
  Author: Haohai Wen <haohai.wen at intel.com>
  Date:   2022-11-23 (Wed, 23 Nov 2022)

  Changed paths:
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-load-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-load-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-load-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll

  Log Message:
  -----------
  [CostModel][X86] Add CostKinds test coverage for shufflevector instruction

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D138485