[all-commits] [llvm/llvm-project] 95ef00: [RISCV][NFC] Mark rs1 in most memory instructions ...

[dybv-sc via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95ef005230e9f793aeb84e2f5ee58571698aace6
      https://github.com/llvm/llvm-project/commit/95ef005230e9f793aeb84e2f5ee58571698aace6
  Author: Dmitry Bushev <dmitry.bushev at syntacore.com>
  Date:   2022-11-22 (Tue, 22 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV][NFC] Mark rs1 in most memory instructions as memory operand.

Marking rs1 (memory offset base) as memory operand provides additional
semantic value to this operand that can be used by different tools
(e.g. llvm-exegesis).

This change does not affect neigther Isel nor assembler. However it
required some tweaks in tablegen compressed inst emmiter.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D136847