[all-commits] [llvm/llvm-project] 24810a: [RISCV] Add isel patterns to select slli+shXadd.uw.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24810acb629d05eb3253a52a7220486b5b1d6791
      https://github.com/llvm/llvm-project/commit/24810acb629d05eb3253a52a7220486b5b1d6791
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-21 (Mon, 21 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to select slli+shXadd.uw.

This matches what we get for something like.
%0 = shl i32 %x, C
%1 = zext i32 %0 to i64
%2 = getelementptr i32, ptr %y, %1

The shift before the zext and the shift implied by the GEP get
combined with an AND after them. We need to split it back into
2 shifts so we can fold one into shXadd.uw.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137886