[all-commits] [llvm/llvm-project] dd9a90: [X86] Remove unnecessary XGETBV instruction overri...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dd9a900a50f41dc5143103406b8eb00664ff96b4
      https://github.com/llvm/llvm-project/commit/dd9a900a50f41dc5143103406b8eb00664ff96b4
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-11-20 (Sun, 20 Nov 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td

  Log Message:
  -----------
  [X86] Remove unnecessary XGETBV instruction overrides from znver1/znver2 models

Reported by D138359 - znver models already treats all WriteSystem sched instructions as microcoded


  Commit: 4695f5982a9da45dcb89ce013f92bb898c6292b6
      https://github.com/llvm/llvm-project/commit/4695f5982a9da45dcb89ce013f92bb898c6292b6
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-11-20 (Sun, 20 Nov 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleBdVer2.td

  Log Message:
  -----------
  [X86] Remove unnecessary SHLD32rri8/SHRD16rri8 instruction override from bdver2 model

Reported by D138359 - the override matches the WriteSHDrri base sched def


Compare: https://github.com/llvm/llvm-project/compare/6a8fabf5c316...4695f5982a9d