[all-commits] [llvm/llvm-project] f8c63a: [SDAG] Allow scalable vectors in ComputeNumSignBits

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f8c63a7fbf50fb5883bd566c7539d0ac18c7700f
      https://github.com/llvm/llvm-project/commit/f8c63a7fbf50fb5883bd566c7539d0ac18c7700f
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-11-18 (Fri, 18 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

  Log Message:
  -----------
  [SDAG] Allow scalable vectors in ComputeNumSignBits

This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137141