[all-commits] [llvm/llvm-project] 98e342: [RISCV][llvm-mca] Use LMUL Instruments to provide ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 98e342dca23729dd4e9cdc5f25c647d617b94283
      https://github.com/llvm/llvm-project/commit/98e342dca23729dd4e9cdc5f25c647d617b94283
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2022-11-18 (Fri, 18 Nov 2022)

  Changed paths:
    M llvm/docs/CommandGuide/llvm-mca.rst
    M llvm/include/llvm/MC/TargetRegistry.h
    M llvm/include/llvm/MCA/CustomBehaviour.h
    M llvm/include/llvm/MCA/InstrBuilder.h
    M llvm/lib/MCA/CustomBehaviour.cpp
    M llvm/lib/MCA/InstrBuilder.cpp
    M llvm/lib/Target/RISCV/CMakeLists.txt
    A llvm/lib/Target/RISCV/MCA/CMakeLists.txt
    A llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
    A llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/tools/llvm-mca/CodeRegion.cpp
    M llvm/tools/llvm-mca/CodeRegion.h
    M llvm/tools/llvm-mca/CodeRegionGenerator.cpp
    M llvm/tools/llvm-mca/CodeRegionGenerator.h
    M llvm/tools/llvm-mca/llvm-mca.cpp
    M llvm/unittests/tools/llvm-mca/MCATestBase.cpp
    M llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp

  Log Message:
  -----------
  [RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV

On x86 and AArch, SIMD instructions encode all of the scheduling information in the instruction
itself. For example, VADD.I16 q0, q1, q2 is a neon instruction that operates on 16-bit integer
elements stored in 128-bit Q registers, which leads to eight 16-bit lanes in parallel. This kind
of information impacts how the instruction takes to execute and what dependencies this may cause.

On RISCV however, the data that impacts scheduling is encoded in CSR registers such as vtype or
vl, in addition with the instruction itself. But MCA does not track or use the data in these
registers. This patch fixes this problem by introducing Instruments into MCA.

* Replace `CodeRegions` with `AnalysisRegions`
* Add `Instrument` and `InstrumentManager`
* Add `InstrumentRegions`
* Add RISCV Instrument and `InstrumentManager`
* Parse `Instruments` in driver
* Use instruments to override schedule class
* RISCV use lmul instrument to override schedule class
* Fix unit tests to pass empty instruments
* Add -ignore-im clopt to disable this change

A prior version of this patch was commited in 5e82ee537321. 2323a4ee610f reverted
that change because the unit test files caused build errors. The change with fixes
were committed in b88b8307bf9e but reverted once again e8e92c8313a0 due to more
build errors.

This commit adds the prior changes and fixes the build error.

Differential Revision: https://reviews.llvm.org/D137440