[all-commits] [llvm/llvm-project] 32bd75: PEI should be able to use backward walk in replace...

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32bd75716c27d1a094c2436529b596ce1547f6eb
      https://github.com/llvm/llvm-project/commit/32bd75716c27d1a094c2436529b596ce1547f6eb
  Author: Alexander Timofeev <alexander.timofeev at amd.com>
  Date:   2022-11-18 (Fri, 18 Nov 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/R600RegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/ARC/ARCRegisterInfo.h
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    M llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
    M llvm/lib/Target/ARM/ThumbRegisterInfo.h
    M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
    M llvm/lib/Target/AVR/AVRRegisterInfo.h
    M llvm/lib/Target/BPF/BPFRegisterInfo.cpp
    M llvm/lib/Target/BPF/BPFRegisterInfo.h
    M llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
    M llvm/lib/Target/CSKY/CSKYRegisterInfo.h
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
    M llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
    M llvm/lib/Target/Lanai/LanaiRegisterInfo.h
    M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
    M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
    M llvm/lib/Target/M68k/M68kRegisterInfo.cpp
    M llvm/lib/Target/M68k/M68kRegisterInfo.h
    M llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
    M llvm/lib/Target/MSP430/MSP430RegisterInfo.h
    M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
    M llvm/lib/Target/Mips/MipsRegisterInfo.h
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.h
    M llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
    M llvm/lib/Target/Sparc/SparcRegisterInfo.h
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
    M llvm/lib/Target/VE/VERegisterInfo.cpp
    M llvm/lib/Target/VE/VERegisterInfo.h
    M llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
    M llvm/lib/Target/XCore/XCoreRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/frame-index.mir
    M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/unittests/CodeGen/MFCommon.inc

  Log Message:
  -----------
  PEI should be able to use backward walk in replaceFrameIndicesBackward.

The backward register scavenger has correct register
liveness information. PEI should leverage the backward register scavenger.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D137574