[all-commits] [llvm/llvm-project] 2e02f0: [AArch64][SME2] Remove vector constraints from zip...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e02f007a27310abaea60f7749093c95e61c813a
      https://github.com/llvm/llvm-project/commit/2e02f007a27310abaea60f7749093c95e61c813a
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-11-18 (Fri, 18 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/SMEInstrFormats.td

  Log Message:
  -----------
  [AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes

The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.

Differential Revision: https://reviews.llvm.org/D138288