[all-commits] [llvm/llvm-project] 7e15ea: [RISCV] Add a DAG combine to pre-promote (i1 (trun...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e15ea102f10061b47b43e230b6841e8e1274d22
      https://github.com/llvm/llvm-project/commit/7e15ea102f10061b47b43e230b6841e8e1274d22
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-16 (Wed, 16 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Add a DAG combine to pre-promote (i1 (truncate (i32 (srl X, Y)))) with Zbs on RV64.

Type legalization will want to turn (srl X, Y) into RISCVISD::SRLW,
which will prevent us from using a BEXT instruction.

This is similar to what we do for (i32 (and (srl X, Y), 1)).