[all-commits] [llvm/llvm-project] 49510c: [AArch64] Mark all instructions that read/write FP...

[john-brawn-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 49510c50200cf58c9f2dedf4e4ab36a16503878e
      https://github.com/llvm/llvm-project/commit/49510c50200cf58c9f2dedf4e4ab36a16503878e
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-11-16 (Wed, 16 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
    M llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
    M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
    M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
    M llvm/test/CodeGen/AArch64/machine-combiner-instr-fmf.mir
    M llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
    M llvm/test/CodeGen/AArch64/machine-combiner.mir
    M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    M llvm/test/CodeGen/AArch64/strict-fp-opt.ll
    M llvm/test/CodeGen/AArch64/taildup-inst-dup-loc.mir
    M llvm/test/CodeGen/AArch64/wineh-frame1.mir
    M llvm/test/CodeGen/AArch64/wineh-frame2.mir
    M llvm/test/CodeGen/AArch64/wineh-frame4.mir
    M llvm/test/CodeGen/AArch64/wineh2.mir
    M llvm/test/CodeGen/AArch64/wineh3.mir
    M llvm/test/CodeGen/AArch64/wineh4.mir
    M llvm/test/CodeGen/AArch64/wineh8.mir
    M llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
    M llvm/test/DebugInfo/COFF/AArch64/codeview-b-register.mir
    M llvm/test/DebugInfo/COFF/AArch64/codeview-h-register.mir

  Log Message:
  -----------
  [AArch64] Mark all instructions that read/write FPCR as doing so

All instructions that can raise fp exceptions also read FPCR, with the
only other instructions that interact with it being the MSR/MRS to
write/read FPCR.

Introducing an FPCR register also requires adjusting
invalidateWindowsRegisterPairing in AArch64FrameLowering.cpp to use
the encoded value of registers instead of their enum value, as the
enum value is based on the alphabetical order of register names and
now FPCR is placed between FP and LR.

This change unfortunately means a large number of mir tests need to
be adjusted due to instructions now requiring an implicit fpcr operand
to be present.

Differential Revision: https://reviews.llvm.org/D121929