[all-commits] [llvm/llvm-project] a214c5: [RISCV] Don't use zero-stride vector load for gath...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a214c521f8763b36dd400b89017f74ad5ae4b6c7
      https://github.com/llvm/llvm-project/commit/a214c521f8763b36dd400b89017f74ad5ae4b6c7
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2022-11-16 (Wed, 16 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

  Log Message:
  -----------
  [RISCV] Don't use zero-stride vector load for gather if not optimized

We may form a zero-stride vector load when lowering gather to strided
load. As what D137699 has done, we use `load+splat` for this form if
there is no optimized implementation.
We restrict this to unmasked loads currently in consideration of the
complexity of hanlding all falses masks.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137931