[all-commits] [llvm/llvm-project] f38791: [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f387918dd8549331a4f60df70cccd9558eca8df1
      https://github.com/llvm/llvm-project/commit/f387918dd8549331a4f60df70cccd9558eca8df1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-15 (Tue, 15 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
    M llvm/test/CodeGen/ARM/load-combine-big-endian.ll
    M llvm/test/CodeGen/ARM/load-combine.ll
    M llvm/test/CodeGen/Mips/bswap.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

  Log Message:
  -----------
  [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask constants used by BSWAP expansion.

We can reuse constants if we use SRL followed by AND and AND followed by SHL.
Similar was done to bitreverse previously.

Differential Revision: https://reviews.llvm.org/D138045