[all-commits] [llvm/llvm-project] 868160: [SiFive] Minimal architecture support for xsfvcp.

Mon Nov 14 23:54:07 PST 2022

  Branch: refs/heads/sifive/llvm-project-with-VCIX
  Home:   https://github.com/llvm/llvm-project
  Commit: 868160ad5f7ced95ab55f7037efd4b39fc8ac7e7
      https://github.com/llvm/llvm-project/commit/868160ad5f7ced95ab55f7037efd4b39fc8ac7e7
  Author: Nelson Chu <nelson.chu at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [SiFive] Minimal architecture support for xsfvcp.

This patch just let clang/llvm recognizes the xsfvcp extension name with
default 0.1 version, but we actually havn't supported it.  The imply rule
of xsfvcp isn't clear for now, so just ignore it.

  Commit: 92016f97364fec11d7583c4d5079acfec40a8e24
      https://github.com/llvm/llvm-project/commit/92016f97364fec11d7583c4d5079acfec40a8e24
  Author: Nelson Chu <nelson.chu at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
    A llvm/test/MC/RISCV/rvv/xsfvcp.s

  Log Message:
  -----------
  [SiFive] Support assembler and dis-assembler for xsfvcp extension.

I can not reuse the defined RVVconstraints directly, since we are used to
assume the operand order is rd, rs2, and then rs1.  But for the VCIX
instructions, the first operand should be the uimm2 payload, rather than
the rd.  I have two options here, one is to define new RVVconstraints,
but that will need more bits in the RVVConstraint.  So I choose another
easy way, to handle the VCIX constraints specially in the validateInstruction,
but reuse the defined VS2Constraint and VS1Constraint.

Architecture spec: https://docs.google.com/document/d/1t7KkKILmmQ0mAgnDLj1s2ks-UXkMR9cWOHuIsewovPE/edit

  Commit: 229482fe29e7adae93da36fb708c25075fbd9be6
      https://github.com/llvm/llvm-project/commit/229482fe29e7adae93da36fb708c25075fbd9be6
  Author: Nelson Chu <nelson.chu at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-x-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
    A llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll

  Log Message:
  -----------
  [SiFive] Support LLVM IR intrinsics for xsfvcp extension.

The sf.vc.x and sf.vc.i intrinsics don't have any vector types in the output
and inputs, but the intrinsic spec said that we still need to add vetvli for
them.  Therefore, we need to encode the VTYPE to these IR names.

Architecture spec: https://docs.google.com/document/d/1t7KkKILmmQ0mAgnDLj1s2ks-UXkMR9cWOHuIsewovPE/edit

Intrinsic spec: https://github.com/sifive/rvv-intrinsic-internal/blob/master/rvv_intrinsic_gen/overloaded_intrinsic_funcs/11_sifive_custom_vector_extension_functions.md#vcix-instructions-xsfvcp

  Commit: dcc9a96ded6c3b6327975556b685d7562bc4827f
      https://github.com/llvm/llvm-project/commit/dcc9a96ded6c3b6327975556b685d7562bc4827f
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M clang/include/clang/Support/RISCVVIntrinsicUtils.h
    M clang/lib/Sema/SemaRISCVVectorLookup.cpp
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [SiFive][RISCV] Add SiFive extension support

  Commit: 53f74164eccec516994e4ba4824e2a8841702f88
      https://github.com/llvm/llvm-project/commit/53f74164eccec516994e4ba4824e2a8841702f88
  Author: Nelson Chu <nelson.chu at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/include/clang/Support/RISCVVIntrinsicUtils.h
    M clang/lib/Support/RISCVVIntrinsicUtils.cpp
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-x-rv64.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-x.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xv-rv64.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xv.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvv-rv64.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvv.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvw.c

  Log Message:
  -----------
  [SiFive] Support C intrinsics for xsfvcp extension.

There are two problems here,

The first problem is that - the payloads are defined as "const int", so I
have to update our RISCVVEmitter, to recognized "i" and it will be always
32-bit Signed integer.

The other problem is that - the sf.vc.x and sf.vc.i intrinsic don't have any
vector types used for their input and output, but the intrinsic names need
"Uv" as the suffix, otherwise we don't know how to add vetveli for them.
The current RISCVVEmitter reports errors for the above case, maybe we should
also update the Emitter, but I figured that we could define workarounds like
the follows,

sf_vc_x_se_u8m1  : RVVVCIXBuiltinSet<"", "0KiKiUvUe", "c", [0, 3]>;
sf_vc_x_se_u16m1 : RVVVCIXBuiltinSet<"", "0KiKiUvUe", "s", [0, 3]>;
sf_vc_x_se_u32m1 : RVVVCIXBuiltinSet<"", "0KiKiUvUe", "i", [0, 3]>;
sf_vc_x_se_u64m1  : RVVVCIXBuiltinSet<"", "0KiKiUvUe", "l", [0, 3]>;

Not sure if the solution is acceptable, but it could work as expected.

Architecture spec: https://docs.google.com/document/d/1t7KkKILmmQ0mAgnDLj1s2ks-UXkMR9cWOHuIsewovPE/edit

Intrinsic spec: https://github.com/sifive/rvv-intrinsic-internal/blob/master/rvv_intrinsic_gen/overloaded_intrinsic_funcs/11_sifive_custom_vector_extension_functions.md#vcix-instructions-xsfvc

  Commit: 04b3c29bd2a62e57aa2e4a5054e7b810360f3c33
      https://github.com/llvm/llvm-project/commit/04b3c29bd2a62e57aa2e4a5054e7b810360f3c33
  Author: Nelson Chu <nelson.chu at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M clang/lib/Sema/SemaChecking.cpp
    A clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-index-out-of-range.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-x-rv64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-x.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xv-rv64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvv-rv64.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/xsfvcp-xvw.c

  Log Message:
  -----------
  [SiFive][Clang] Added index checks for VCIX intrinsics.

[SCT-1484] [VCIX] ICE when VCIX intrinsic give non immediate value to immediate fields.
https://sifive.atlassian.net/browse/SCT-1484

[RVV intrinsics spec]
https://github.com/sifive/rvv-intrinsic-internal/blob/master/rvv_intrinsic_gen/overloaded_intrinsic_funcs/11_sifive_custom_vector_extension_functions.md

Compare: https://github.com/llvm/llvm-project/compare/868160ad5f7c%5E...04b3c29bd2a6