[all-commits] [llvm/llvm-project] dde842: [RISCV] Expand i32 abs to negw+max at isel.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dde8423f21fb09c77b83d1ec50d5fff6bb940586
      https://github.com/llvm/llvm-project/commit/dde8423f21fb09c77b83d1ec50d5fff6bb940586
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Expand i32 abs to negw+max at isel.

This adds a RISCVISD::ABSW to remember that we started with an i32
abs. Previously we used a DAG combine of (sext_inreg (abs)) to
delay emitting a freeze from type legalization in order to make
ComputeNumSignBits optimizations work on other promoted nodes.

This new approach always uses negw+max even if the result doesn't
need to be sign extended. This helps the RISCVSExtWRemoval pass
if the sext.w is in another basic block.