[all-commits] [llvm/llvm-project] 13e32a: [RISCV] Improve use of PACK instruction on rv64.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13e32a8a3c95b23af51f081865db1bd259d269a4
      https://github.com/llvm/llvm-project/commit/13e32a8a3c95b23af51f081865db1bd259d269a4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV] Improve use of PACK instruction on rv64.

Handle the case where the lower bits come from a zero extending
load or other operation with known zero bits.


  Commit: 637ed52d9d74e7ce4f272383852c9f133be3008d
      https://github.com/llvm/llvm-project/commit/637ed52d9d74e7ce4f272383852c9f133be3008d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32zbkb.ll

  Log Message:
  -----------
  [RISCV] Remove old test case. NFC

This seemed to be testing a pattern for an RV64 Zbp instruction, but
on RV32. On RV32, it's just swizzling registers so isn't very
interesting.


Compare: https://github.com/llvm/llvm-project/compare/d7c142795318...637ed52d9d74