[all-commits] [llvm/llvm-project] 3ac93d: [RISCV] Add another PACKH pattern.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ac93d1f2fdad2d9e0fead48911f97c990fb5a69
      https://github.com/llvm/llvm-project/commit/3ac93d1f2fdad2d9e0fead48911f97c990fb5a69
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-13 (Sun, 13 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV] Add another PACKH pattern.

This handles the case where the upper bits are zeroed with an AND
after the OR.


  Commit: 3b759798067f0f9227b8b14c1f24701dbcd3df89
      https://github.com/llvm/llvm-project/commit/3b759798067f0f9227b8b14c1f24701dbcd3df89
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-13 (Sun, 13 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV] Add PACKH/PACKW/PACK to hasAllNBitUsers.


Compare: https://github.com/llvm/llvm-project/compare/d709888bdeea...3b759798067f