[all-commits] [llvm/llvm-project] 1f2588: [RISCV] Add PACKW and PACKH to isSignExtendingOpW ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f25888712cb757854c45e3070178968cdd50371
      https://github.com/llvm/llvm-project/commit/1f25888712cb757854c45e3070178968cdd50371
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-13 (Sun, 13 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

  Log Message:
  -----------
  [RISCV] Add PACKW and PACKH to isSignExtendingOpW in RISCVSExtWRemoval.

PACKW sign extends like other W instructions.
PACKH zeroes bits 63:16 which means bits 63:31 are all zero.