[all-commits] [llvm/llvm-project] 3acbad: [NFC][AArch64]Precommit test cases to show ORR is ...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3acbaddd43d8340257ad79a3514865c9758612c2
      https://github.com/llvm/llvm-project/commit/3acbaddd43d8340257ad79a3514865c9758612c2
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-11-11 (Fri, 11 Nov 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll

  Log Message:
  -----------
  [NFC][AArch64]Precommit test cases to show ORR is better when one operand is a shift of the other operand

In `bfi-not-orr` tests, bfi/bfxil are better since they simplifies away two instructions (extracting bits into destination directly)

In `orr-not-bfi` tests, orr is better since both orr and bfm would simplify away one instruction (the shl node), orr has higher throughput and shorter latency than bfm.


  Commit: 0f9ef8b18055c9f7ca534fab24f74266331ec3e5
      https://github.com/llvm/llvm-project/commit/0f9ef8b18055c9f7ca534fab24f74266331ec3e5
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-11-11 (Fri, 11 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll

  Log Message:
  -----------
  [AArch64] Select BFI/BFXIL to ORR with shifted operand when one operand is the left or right shift of another operand

Use right shift [1] as an example
- Before, bfxil is generated (https://godbolt.org/z/EfzWMszPn)
- After, orr with right-shifted operand is generated (added test cases in `CodeGen/AArch64/bitfield-insert.ll`)

[1]
```
define i64 @test_orr_not_bfxil_i64(i64 %0) {
  %2 = and i64 %0, 1044480 ; 0xff000
  %3 = lshr i64 %2, 12
  %4 = or i64 %2, %3
  ret i64 %4
}
```

Differential Revision: https://reviews.llvm.org/D137689


Compare: https://github.com/llvm/llvm-project/compare/5ab1a8aef454...0f9ef8b18055