[all-commits] [llvm/llvm-project] ffb109: [AArch64][SVE] Support logical operation BIC with ...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ffb109b6852d248c9d2e3202477dccf20aac7151
      https://github.com/llvm/llvm-project/commit/ffb109b6852d248c9d2e3202477dccf20aac7151
  Author: zhongyunde <zhongyunde at huawei.com>
  Date:   2022-11-11 (Fri, 11 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll
    A llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir

  Log Message:
  -----------
  [AArch64][SVE] Support logical operation BIC with DestructiveBinary patterns

Logical operation BIC with DestructiveBinary patterns is temporarily removed as
causes an assert (commit 3c382ed71f15), so try to fix that.
The most significant being that for pseudo instructions that do not have real instructions (including movpfx'd ones) that cover all combinations of register allocation, their expansion will be broken. This is the main reason the zeroing is an experimental feature because it has known bugs.
So we add an extra LSL for movprfx expand BIC_ZPZZ_ZERO A, P, A, A when necessary.
  movprfx	z0.s, p0/z, z0.s
  lsl z0.b, p0/m, z0.b, #0
  bic	z0.s, p0/m, z0.s, z0.s

Depends on D88595