[all-commits] [llvm/llvm-project] ecab1b: [AArch64]SME2 Multi vector Sel Load and Store ins...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecab1bc0dcdc04ec863f7aa3eaa5daad8232ba65
      https://github.com/llvm/llvm-project/commit/ecab1bc0dcdc04ec863f7aa3eaa5daad8232ba65
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2022-11-10 (Thu, 10 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME2/add-diagnostics.s
    M llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
    M llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
    A llvm/test/MC/AArch64/SME2/ld1b.s
    A llvm/test/MC/AArch64/SME2/ld1d.s
    A llvm/test/MC/AArch64/SME2/ld1h.s
    A llvm/test/MC/AArch64/SME2/ld1w.s
    A llvm/test/MC/AArch64/SME2/ldnt1b.s
    A llvm/test/MC/AArch64/SME2/ldnt1d.s
    A llvm/test/MC/AArch64/SME2/ldnt1h.s
    A llvm/test/MC/AArch64/SME2/ldnt1w.s
    A llvm/test/MC/AArch64/SME2/sel-diagnostics.s
    A llvm/test/MC/AArch64/SME2/sel.s
    M llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
    A llvm/test/MC/AArch64/SME2/st1b
    A llvm/test/MC/AArch64/SME2/st1b.s
    A llvm/test/MC/AArch64/SME2/st1d.s
    A llvm/test/MC/AArch64/SME2/st1h.s
    A llvm/test/MC/AArch64/SME2/st1w.s
    A llvm/test/MC/AArch64/SME2/stnt1b.s
    A llvm/test/MC/AArch64/SME2/stnt1d.s
    A llvm/test/MC/AArch64/SME2/stnt1h.s
    A llvm/test/MC/AArch64/SME2/stnt1w.s
    M llvm/test/MC/AArch64/SME2/sub-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st2b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st2d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st2h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st2w-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st3b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st3d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st3h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st3w-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st4b-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st4d-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st4h-diagnostics.s
    M llvm/test/MC/AArch64/SVE/st4w-diagnostics.s
    M llvm/test/MC/AArch64/SVE2/ext-diagnostics.s
    M llvm/test/MC/AArch64/SVE2/splice-diagnostics.s
    M llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s
    M llvm/test/MC/AArch64/neon-diagnostics.s

  Log Message:
  -----------
  [AArch64]SME2 Multi vector Sel Load and Store  instructions

This patch adds the assembly/disassembly for the following instruction:

   SEL: Multi-vector conditionally select elements from two vectors
        for 2 and 4 registers

Non-constiguous load with stride resgisters:

  LD1B (scalar + immediate): Contiguous load of bytes to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load of bytes to multiple strided vectors (scalar index).
  LD1D (scalar + immediate): Contiguous load of doublewords to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load of doublewords to multiple strided vectors (scalar index).
  LD1H (scalar + immediate): Contiguous load of halfwords to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load of halfwords to multiple strided vectors (scalar index).
  LD1W (scalar + immediate): Contiguous load of words to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load of words to multiple strided vectors (scalar index).

  LDNT1B (scalar + immediate): Contiguous load non-temporal of bytes to multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous load non-temporal of bytes to multiple strided vectors (scalar index).
  LDNT1D (scalar + immediate): Contiguous load non-temporal of doublewords to multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous load non-temporal of doublewords to multiple strided vectors (scalar index).
  LDNT1H (scalar + immediate): Contiguous load non-temporal of halfwords to multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous load non-temporal of halfwords to multiple strided vectors (scalar index).
  LDNT1W (scalar + immediate): Contiguous load non-temporal of words to multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous load non-temporal of words to multiple strided vectors (scalar index).

Non-constiguous store with stride resgisters:

  ST1B (scalar + immediate): Contiguous store of bytes from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store of bytes from multiple strided vectors (scalar index).
  ST1D (scalar + immediate): Contiguous store of doublewords from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store of doublewords from multiple strided vectors (scalar index).
  ST1H (scalar + immediate): Contiguous store of halfwords from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store of halfwords from multiple strided vectors (scalar index).
  ST1W (scalar + immediate): Contiguous store of words from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store of words from multiple strided vectors (scalar index).

  STNT1B (scalar + immediate): Contiguous store non-temporal of bytes from multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous store non-temporal of bytes from multiple strided vectors (scalar index).
  STNT1D (scalar + immediate): Contiguous store non-temporal of doublewords from multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous store non-temporal of doublewords from multiple strided vectors (scalar index).
  STNT1H (scalar + immediate): Contiguous store non-temporal of halfwords from multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous store non-temporal of halfwords from multiple strided vectors (scalar index).
  STNT1W (scalar + immediate): Contiguous store non-temporal of words from multiple strided vectors (immediate index).
         (scalar + scalar): Contiguous store non-temporal of words from multiple strided vectors (scalar index).

    The reference can be found here:

        https://developer.arm.com/documentation/ddi0602/2022-09

This patch also adds a new SVE vector list to represent the stride loads/stores
ZPRVectorListStrided and the sets of 2 and 4 ZA registers:
ZZ_[b|h|w|d]_strided and ZZZZ_[b|h|w|d]_strided

Differential Revision: https://reviews.llvm.org/D136172