[all-commits] [llvm/llvm-project] 7d5c8c: [LoongArch] Added spill/reload/copy support for CFRs

[wanglei via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d5c8cb023515efd1d80a9120f27ed5cdb1d1404
      https://github.com/llvm/llvm-project/commit/7d5c8cb023515efd1d80a9120f27ed5cdb1d1404
  Author: wanglei <wanglei at loongson.cn>
  Date:   2022-11-10 (Thu, 10 Nov 2022)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
    M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
    M llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
    A llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll

  Log Message:
  -----------
  [LoongArch] Added spill/reload/copy support for CFRs

1, spill/reload
When a function call is made immediately after a floating point
comparison, the result of the comparison needs to be spilled before
function call and reloaded after the function returns.

2, copy
Support `GPR` to `CFR` and `CFR` to `GRP` copys. Therefore, the correct
register class can be used in the pattern template, and the hard-coding
of mutual coping of `CFR` and `GRP` is eliminated, reducing redundant
comparison instructions.

Note: Since the `COPY` instruction between CFRs is not provided in
LoongArch, we only use `$fcc0` in the register allocation.

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D137004