[all-commits] [llvm/llvm-project] f4f6c6: [RISCV] Add support for static chain

[melonedo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f4f6c63f0df7465b3f4e64e1637405e641f19dc2
      https://github.com/llvm/llvm-project/commit/f4f6c63f0df7465b3f4e64e1637405e641f19dc2
  Author: melonedo <funanzeng at gmail.com>
  Date:   2022-11-09 (Wed, 09 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/ghccc-nest.ll
    A llvm/test/CodeGen/RISCV/nest-register.ll

  Log Message:
  -----------
  [RISCV] Add support for static chain

The static chain parameter is a special parameter that is not passed in the usual argument registers or stack space. For example, in x64 System V ABI it is always passed in R10. Although the ABI of RISCV does not assign a register for this purpose, GCC had support for it on RISC-V a long time ago, and it is exposed via `__builtin_call_with_static_chain` intrinsic, and assign t2 for static chain parameters. This patch also chose t2 for compatibility.

In LLVM, static chain parameters are handled by the `nest` attribute of an argument to a function ([D6332](https://reviews.llvm.org/D6332)), so tests are added to ensure `nest` arguments are handled correctly.

Reviewed By: kito-cheng, MaskRay

Differential Revision: https://reviews.llvm.org/D129106