[all-commits] [llvm/llvm-project] e4e7bd: [AArch64]Combine BFXIL to ORR with right shift for...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e4e7bdebb180ea81aa7927797c20e694ed18bee8
      https://github.com/llvm/llvm-project/commit/e4e7bdebb180ea81aa7927797c20e694ed18bee8
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-11-08 (Tue, 08 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/fcopysign.ll

  Log Message:
  -----------
  [AArch64]Combine BFXIL to ORR with right shift for ISD::OR instruction selection

- This extends the existing helper function 'isWorthFoldingIntoOrrWithLeftShift' into
  'isWorthFoldingIntoOrrWithShift', and encode right-shift imm (the
  encoding of left-shift imm is no-op).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D137465