[all-commits] [llvm/llvm-project] 674a17: MIPS/compiler_rt: use synci to flush icache on r6

[YunQiang Su via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 674a17e9bbe82e8c53952fd94dcd862b17cb2d2f
      https://github.com/llvm/llvm-project/commit/674a17e9bbe82e8c53952fd94dcd862b17cb2d2f
  Author: YunQiang Su <wzssyqa at gmail.com>
  Date:   2022-11-07 (Mon, 07 Nov 2022)

  Changed paths:
    M compiler-rt/lib/builtins/clear_cache.c

  Log Message:
  -----------
  MIPS/compiler_rt: use synci to flush icache on r6

syscall makes it failed to build on mips64 for mipsel:
```
compiler-rt/lib/builtins/clear_cache.c:97:3: error:
call to undeclared function 'syscall'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
```

In this patch, we use `rdhwr` to get synci_step.
If synci_step is zero, it means that the hardware will maintain the coherence. We need to do nothing.
Then for r6+, `synci` is required to keep icache global.
So we can use `synci` to flush icache.
The ISA documents ask a `sync` and a `jr.hb` after `synci`.

For pre-r6, we can use cacheflush libc function, which is same on Linux and FreeBSD.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D135565