[all-commits] [llvm/llvm-project] a9d7b1: [AArch64][SVE2] Add the SVE2.1 quadword variants o...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9d7b18b4a853daa8fecb5d5863af211841de762
      https://github.com/llvm/llvm-project/commit/a9d7b18b4a853daa8fecb5d5863af211841de762
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-11-07 (Mon, 07 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p1/ld1d_q.s
    A llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p1/ld1w_q.s
    A llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p1/st1d_q.s
    A llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p1/st1w_q.s

  Log Message:
  -----------
  [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d

This patch adds the assembly/disassembly for the following instructions:

st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D137245