[all-commits] [llvm/llvm-project] c8be35: [SWP] Recognize mem carried dep with different base

[RoboTux via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c8be35293c82f216e975c56f62ddf9199a22f2e2
      https://github.com/llvm/llvm-project/commit/c8be35293c82f216e975c56f62ddf9199a22f2e2
  Author: Thomas Preud'homme <thomasp at graphcore.ai>
  Date:   2022-11-07 (Mon, 07 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    A llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir

  Log Message:
  -----------
  [SWP] Recognize mem carried dep with different base

The loop-carried dependency detection logic in isLoopCarriedDep relies
on the load and store using the same definition for the base register.
This misses the case of post-increment loads and stores whose base
register are different PHI initialized from the same initial value.

This commit extends the logic to accept the load and store having
different PHI base address provided that they had the same initial value
when entering the loop and are incremented by the same amount in each
loop.

Reviewed By: bcahoon

Differential Revision: https://reviews.llvm.org/D136463