[all-commits] [llvm/llvm-project] 83255c: Recommit [AArch64] Improve codegen for shifted mas...

[chenglin.bi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 83255c4a626df5df539a71fba864c99fcb1cb674
      https://github.com/llvm/llvm-project/commit/83255c4a626df5df539a71fba864c99fcb1cb674
  Author: chenglin.bi <chenglin.bi at linaro.org>
  Date:   2022-11-07 (Mon, 07 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/shift-logic.ll

  Log Message:
  -----------
  Recommit [AArch64] Improve codegen for shifted mask op

The original change compares `APInt` to check the constant is the same or not. But shift amount may have different constant types.
So, this patch change to use `getZExtValue` to compare constant value.

Original comment:
The special case for bit extraction pattern is  `((x >> C) & mask) << C`.
It can be combined to `x & (mask << C)` by return true in isDesirableToCommuteWithShift.

Fix: #56427

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D136014