[all-commits] [llvm/llvm-project] 4830fa: [RISCV] Make sure we always call tryShrinkShlLogic...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4830fa18aac6950d479a413c995c38fff56ac42c
      https://github.com/llvm/llvm-project/commit/4830fa18aac6950d479a413c995c38fff56ac42c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-22 (Sat, 22 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
    M llvm/test/CodeGen/RISCV/shift-and.ll

  Log Message:
  -----------
  [RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.

There was an early out that prevented us from calling this for
(and (sext_inreg (shl X, C1), i32), C2).