[all-commits] [llvm/llvm-project] 1e4f82: [AArch64]SME2 Multi-single vector SVE Destructive ...

CarolineConcatto via All-commits all-commits at lists.llvm.org
Fri Oct 21 06:02:39 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e4f82c2578cf5045ffeda6c425d6d262a401e29
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2022-10-21 (Fri, 21 Oct 2022)

  Changed paths:
    M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    M llvm/test/MC/AArch64/SME2/add-diagnostics.s
    M llvm/test/MC/AArch64/SME2/add.s
    A llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
    A llvm/test/MC/AArch64/SME2/sqdmulh.s
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

This patch adds the assembly/disassembly for the following instructions:
  ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
  SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.
for 2 and 4 ZA SVE registers.

The reference can be found here:


It also adds more size for the multiple register tuple:
  ZZ_b_mul_r,  ZZ_h_mul_r,
  ZZZZ_b_mul_r,  ZZZZ_h_mul_r,
for 8 bits and 16 bits with 2 and 4 ZA registers.

Depends on: D135468

With a fix for Mips for this test:

Differential Revision: https://reviews.llvm.org/D135563

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