[all-commits] [llvm/llvm-project] c98add: [LoongArch] Report error in AsmParser when rd == r...

[Lu Weining via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c98add7a11ff35d42fee860f9c9d301601ff5861
      https://github.com/llvm/llvm-project/commit/c98add7a11ff35d42fee860f9c9d301601ff5861
  Author: Weining Lu <luweining at loongson.cn>
  Date:   2022-10-21 (Fri, 21 Oct 2022)

  Changed paths:
    M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
    M llvm/test/MC/LoongArch/Basic/Integer/invalid64.s

  Log Message:
  -----------
  [LoongArch] Report error in AsmParser when rd == rk or rd == rj for AM* instructions

Do this check because the ISA manual says (edited from the original translation):

> If the AM* instruction has its rd == rj, an Instruction Non-defined Exception will be triggered when the instruction is executed.
>
> If the AM* instruction has its rd == rk, the execution result is unpredictable. It is software's responsibility to avoid this situation.

Note that binutils does the same check except when rd == r0 but this
is undocumented.

Differential Revision: https://reviews.llvm.org/D136076