[all-commits] [llvm/llvm-project] c66426: [RISCV] Remove EEW from some sched classes.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c66426f3a06fa8626b1bd4fb0844aa04a424037c
      https://github.com/llvm/llvm-project/commit/c66426f3a06fa8626b1bd4fb0844aa04a424037c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-20 (Thu, 20 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Remove EEW from some sched classes.

This removes the EEW from unit stride load/store and whole register
load, store, move.

It seems reasonable that implementations of these instructions wouldn't
usually be affected by element width.

We likely need to add LMUL information to our scheduling classes so
I thought it might be good to remove a few before they got multiplied
by LMUL.

Reviewed By: reames, michaelmaitland

Differential Revision: https://reviews.llvm.org/D135992