[all-commits] [llvm/llvm-project] 2ecbe8: [AArch64] SME2 Single-multi vector ternary int/FP ...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ecbe8c38c99174e91f3f4627c01ea215af527ed
      https://github.com/llvm/llvm-project/commit/2ecbe8c38c99174e91f3f4627c01ea215af527ed
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2022-10-19 (Wed, 19 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    A llvm/test/MC/AArch64/SME2/add-diagnostics.s
    A llvm/test/MC/AArch64/SME2/add.s
    A llvm/test/MC/AArch64/SME2/directive-arch.s
    A llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
    A llvm/test/MC/AArch64/SME2/fmla.s
    A llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
    A llvm/test/MC/AArch64/SME2/fmls.s
    A llvm/test/MC/AArch64/SME2/sub-diagnostics.s
    A llvm/test/MC/AArch64/SME2/sub.s

  Log Message:
  -----------
  [AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers

This patch adds the assembly/disassembly for the following instructions:

For INT:
    ADD(array results, multiple and single vector): Add replicated single
        vector to multi-vector with ZA array vector results.
    SUB(array results, multiple and single vector): Subtract replicated single
        vector from multi-vector with ZA array vector results.
For FP:
    FMLA (multiple and single vector): Multi-vector floating-point fused
          multiply-add by vector.
    FMLS (multiple and single vector): Multi-vector floating-point
          multiply-subtract long by vector.
The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

The Matriz Operand has 2 new sizes 32(.s) and 64(.d) bits
(MatrixOp32 and MatrixOp64)

Depends on: D135448

Depends on:  D135952

Differential Revision: https://reviews.llvm.org/D135455