[all-commits] [llvm/llvm-project] 34d18f: [AArch64] Enhance bit-field-positioning op matcher...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34d18fd241abafdf0436cbceebdeff2ecf685ae2
      https://github.com/llvm/llvm-project/commit/34d18fd241abafdf0436cbceebdeff2ecf685ae2
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-10-18 (Tue, 18 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll

  Log Message:
  -----------
  [AArch64] Enhance bit-field-positioning op matcher to see through 'any_extend' for pattern 'and(any_extend(shl(val, N)), shifted-mask)'

Before this patch (and refactor patch D135843), isBitfieldPositioningOp won't handle "and(any_extend(shl(val, N), shifted-mask)" (bail out if AND op is not SHL)

After this patch, isBitfieldPositioningOp will see through "any_extend" to find "shl" to find possible bit-field-positioning nodes.

https://gcc.godbolt.org/z/3ncGKbGW6 is a four-liner LLVM IR that could be optimized to UBFIZ (see added test case test_and_extended_shift_with_imm in llvm/test/CodeGen/AArch64/bitfield-insert.ll). One existing test case also improves.

Differential Revision: https://reviews.llvm.org/D135852