[all-commits] [llvm/llvm-project] 4467c7: [clang][RISCV] Set vscale_range attribute based on...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4467c781d7bbf25a3b89a25ccbc0382731f51322
      https://github.com/llvm/llvm-project/commit/4467c781d7bbf25a3b89a25ccbc0382731f51322
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-10-17 (Mon, 17 Oct 2022)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    A clang/test/CodeGen/riscv-vector-bits-vscale-range.c

  Log Message:
  -----------
  [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

This follows the path that AArch64 SVE has taken. Doing this via a function attribute set in the frontend is basically a workaround for the fact that several analyzes which need the information (i.e. known bits, lvi, scev) can't easily use TTI without significant amounts of plumbing changes.

This patch hard codes "v" numbers, and directly follows the SVE precedent as a result. In a follow up, I hope to drive this from RISCVISAInfo.h/cpp instead, but the MinVLen number being returned from that interface seemed to always be 0 (which is wrong), and I haven't figured out what's going wrong there.

Differential Revision: https://reviews.llvm.org/D135894