[all-commits] [llvm/llvm-project] db0286: [AArch64]Enhance 'isBitfieldPositioningOp' to find...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db0286a09626a3a29ceacbe95a1a05004f62242c
      https://github.com/llvm/llvm-project/commit/db0286a09626a3a29ceacbe95a1a05004f62242c
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-10-17 (Mon, 17 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
    M llvm/test/CodeGen/AArch64/pr58350.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll

  Log Message:
  -----------
  [AArch64]Enhance 'isBitfieldPositioningOp' to find pattern (shl(and(val,mask), N).

Before this patch (and D135844)

- Given DAG node shl(op, N), isBitfieldPositioningOp uses (optionally shifted [1] ) op as the Src (least significant bits of Src are inserted into DstLSB of Dst node).

After this patch

- If op is and(val, mask), isBitfieldPositioningOp tries to see through and and find if val is a simpler source than op.

It helps in a similar (probably symmetric) way how isSeveralBitsExtractOpFromShr [2] optimizes isBitfieldExtractOpFromShr

Existing test cases are improved without regressions.

[1] https://github.com/llvm/llvm-project/blob/cbd8464595220b5ea76c70ac9965d84970c4b712/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp#L2546
[2] https://github.com/llvm/llvm-project/blob/cbd8464595220b5ea76c70ac9965d84970c4b712/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp#L2057

Differential Revision: https://reviews.llvm.org/D135850