[all-commits] [llvm/llvm-project] e68b0d: [RISCV] Match (select C, -1, X)->(or -C, X) during...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e68b0d587581e68e04c155f5f319c22348f1e2b5
      https://github.com/llvm/llvm-project/commit/e68b0d587581e68e04c155f5f319c22348f1e2b5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-13 (Thu, 13 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/min-max.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/uadd_sat.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/usub_sat.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

  Log Message:
  -----------
  [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect

Same with (select C, X, -1), (select C, 0, X), and (select C, X, 0).

There's a DAGCombine after we turn the select into select_cc, but
that may introduce a setcc that didn't previously exist. We could
add more DAGCombines to remove the extra setcc, but this seemed lower
effort.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135833