[all-commits] [llvm/llvm-project] 1c41d0: [RISCV] Use branchless form for selects with 0 in ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c41d0cb62c2637b90a3ae954603af7ba9984975
      https://github.com/llvm/llvm-project/commit/1c41d0cb62c2637b90a3ae954603af7ba9984975
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-10-12 (Wed, 12 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/compress-opt-select.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/usub_sat.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

  Log Message:
  -----------
  [RISCV] Use branchless form for selects with 0 in either arm

Continuing the theme of adding branchless lowerings for simple selects, this time handle the 0 arm case. This is very common for various umin idioms, etc..

Differential Revision: https://reviews.llvm.org/D135600