[all-commits] [llvm/llvm-project] 1bdf21: [RISCV] Use mask/tail agnostic if tied source is I...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1bdf21d55ca70c2f988476f11c49dfba72b6e03a
      https://github.com/llvm/llvm-project/commit/1bdf21d55ca70c2f988476f11c49dfba72b6e03a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-11 (Tue, 11 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

  Log Message:
  -----------
  [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.

If the source is implicit_def, the register allocator won't have
any constraint on what register it picks for the destination. This
doesn't give the user much control of what register is being used.

So in my mind that means the only reason to honor the policy operand
is to control what policy is used in vsetvli to maybe avoid a vtype
change. Given the other optimizations we do on the policy field, I
don't think allowing the user this control is reliable.

Therefore, I think we should use agnostic policies if the source is
undef.

This should give better performance on some CPUs for VP intrinsics where
there is no merge operand and the backend adds IMPLICIT_DEF to the instruction.

Differential Revision: https://reviews.llvm.org/D135396