[all-commits] [llvm/llvm-project] 42b707: Reland "[Clang][LoongArch] Add inline asm support ...

[Lu Weining via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 42b70793a1df473be9c78b4141d3f3cedcbac988
      https://github.com/llvm/llvm-project/commit/42b70793a1df473be9c78b4141d3f3cedcbac988
  Author: Weining Lu <luweining at loongson.cn>
  Date:   2022-10-11 (Tue, 11 Oct 2022)

  Changed paths:
    M clang/lib/Basic/Targets/LoongArch.cpp
    M clang/lib/Basic/Targets/LoongArch.h
    M clang/test/CodeGen/LoongArch/inline-asm-constraints.c
    M llvm/include/llvm/IR/InlineAsm.h
    M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
    M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    A llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
    A llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
    A llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
    A llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
    M llvm/test/CodeGen/X86/callbr-asm-kill.mir

  Log Message:
  -----------
  Reland "[Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC"

Reference: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

k: A memory operand whose address is formed by a base register and
(optionally scaled) index register.

m: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as st.w and ld.w.

ZB: An address that is held in a general-purpose register. The offset
is zero.

ZC: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as ll.w and sc.w.

Note:
The INLINEASM SDNode flags in below tests are updated because the new
introduced enum `Constraint_k` is added before `Constraint_m`.
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/X86/callbr-asm-kill.mir

This patch passes `ninja check-all` on a X86 machine with all official
targets and the LoongArch target enabled.

Differential Revision: https://reviews.llvm.org/D134638